Topology | Other Topology |
IC revision | E4 |
This verified reference design provides an overview on how to implement a three-level three-phase SiC based DC:AC grid-tie inverter stage.Higher switching frequency of 50KHz reduces the size of magnetics for the filter design and enables higher power density. The use of SiC MOSFETs with switching loss ensures higher DC bus voltages of up to 1000V and lower switching losses with a peak efficiency of 99 percent. This design is configurable to work as a two-level or three-level inverter.The system is controlled by a single C2000 microcontroller (MCU), TMS320F28379D, which generates PWM waveforms for all power electronic switching devices under all operating modes.
Order Code | Datasheet | Simulation | |
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![]() | 150060GS75000 | SPEC | |
![]() | 150060RS75000 | SPEC | |
![]() | 885012206095 | SPEC | |
![]() | 61300411021 | SPEC PCN pendingDue to a pending PCN there will be a new datasheet revision issued for this order code soon. Please find the actual as well based on valid PCN date the new revision datasheet below. If you have further questions please get in contact with our sales staff. | – |
![]() | 61301621021 | SPEC PCN pendingDue to a pending PCN there will be a new datasheet revision issued for this order code soon. Please find the actual as well based on valid PCN date the new revision datasheet below. If you have further questions please get in contact with our sales staff. | – |
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Order Code | Datasheet | Simulation | Downloads | Status | Product series | λDom typ. (nm) | Emitting Color | λPeak typ. (nm) | IV typ. (mcd) | VF typ. (V) | Chip Technology | 2θ50% typ. (°) | C | Tol. C | VR (V (DC)) | Size | Operating Temperature | DF (%) | RISO | Ceramic Type | L (mm) | W (mm) | Fl (mm) | Pins (pcs) | Rows | H (mm) | Gender | Type | IR (A) | Packaging | Samples |
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