Microchip MCP16701 | Demoboard MCP16701 Reference Design

Description

The MCP16701 is a 2.7V-5.5V input Power Management Integrated Circuit (PMIC) dedicated to FPGA and highend MPU applications. The MCP16701 supports commercial and industrial applications.It can be configured in-circuit directly by the end user to support a very large number of FPGA use cases. Theprogramming interface is I2C, supporting clock rates up to 3.4 MHz.The MCP16701 integrates 13 power channels distributed as eight parallelable 1.5A Buck regulators, four 300mA LDOs, and one low-input/low-output voltage LDO Controller using an external MOSFET.The eight 1.5A Buck regulators can be operated either independently or in parallel to support higher currents,in groups of up to four. The paralleling technique relies on the matching of the power switches’ resistances anddoes not require the complication of an additional current-sharing loop. The part count and solution footprintare also reduced since all paralleled channels share the same inductor, while the required magnetic volume isthe same as in equivalent multiphase architectures.As a result of the pin arrangement, paralleling up to 4 channels allows for a total of 6A output current with therecommended layout.The switching frequency of the Buck channels defaults to 2 MHz, and the switching phases can be alsoprogrammed. Furthermore, the switching frequency can be synchronized to an external clock within the3-5 MHz range. The frequency synchronization technique can achieve zero phase error (after synchronization)between the incoming synchronization clock and the Buck converters’ turn-on switching, such that the timing ofthe switching events can be accurately established.

Features

Features

• Input Voltage: 2.7V to 5.5V
• Eight 1.5A Buck DC-DC Channels
• Four 300 mA High-accuracy LDOs
• One High-accuracy, High-PSRR LDO Controller Using External N-channel MOSFET (SERDES Lanes Supply)
• ±0.8% Output Voltage Accuracy for Bucks (VDD), for VFB ≥ 1V
• -1.5%/+1% Output Voltage Accuracy for the LDO Controller, for VFB ≥ 0.9V
• ±1% Output Voltage Accuracy for LDOs, for VFB ≥ 1.8V
• Directly Parallelable Buck Channels Power Stages – up to 4 – for a Combined Current Capability up to 6A
• Tight Rds(ON) Matching of Parallelable Channels for Good Current Sharing
• Minimum Number of Inductors: Paralleled Buck Channels Share the Same Inductor
• Programmable Output Voltage for all Buck and LDO Channels 0.6V to 3.8V – No External Feedback ResistorsRequired
• 100% Duty Cycle Capability of Buck Channels
• LDO Controller Output Voltage 0.6V to 1.6V/12.5 mV Steps
• Reference Ground (REFGND) Can be Remotely Routed to the Load Ground (Pseudo Remote Sensing)
• Low-Noise Forced-PWM and Light-load High-efficiency Mode Available (Pin-selectable or Bit Control)
• External Synchronization of Switching Frequency, with Accurate Switching-events Time Positioning
• Selectable Phase (0°, 90°, 180° or 270°) for Buck Channels
• Global RESET (nRSTO_A) with Programmable Deassertion Delay
• User-defined RESET (nRSTO_P) with Programmable Deassertion Delay – Ideal for PolarFire FPGA DEVRST_NInterfacing
• 3.4 MHz I2C Interface

Typical applications

• High-Performance MPUs Power Supply Solutions, µC/µP, FPGA, and DSP Power

More information

• Datasheet
• IC product information