Intel STRATIX V GX F1517

Description

The Stratix V GX FPGA development board provides a hardware platform fordeveloping and prototyping high-performance and high-bandwidth application designs. The board provides a wide range of peripherals and memory interfaces to facilitate the development of Stratix V GX FPGA designs.

Two High-Speed Mezzanine Card (HSMC) connectors are available to add additional functionality via a variety of HSMC cards available from both Altera and various partners.

f To see a list of the latest HSMC cards available or to download a copy of the HSMC specification, refer to the Development Board Daughtercards page of the Altera website.

Design advancements and innovations, such as the PCI Express hard IPimplementation, partial reconfiguration, and programmable power technology ensure that designs implemented in the Stratix V GX FPGAs operate faster, with lower power than in previous FPGA families.

Features

• Altera Stratix V FPGA (5SGXEA7K2F40C2N) in the 1517-pin FineLine BGA Package
• 622,000 LEs
• 234,720 adaptive logic modules (ALMs)
• 50-Mbits (Mb) embedded memory
• 36 transceivers (12.5 Gbps)
• 174 full-duplex LVDS channels
• 28 phase locked loops (PLLs)
• 512 18x18-bit multipliers
• 900-mV core voltage
• 696 user I/Os
• 2 PCI Express hard IP blocks
• MAX® V CPLD (5M2210ZF256C4) System Controller in the 256-pin FineLine BGA Package
• 2,210 LEs
• 203 user I/Os
• 1.8-V core voltage
• FPGA Configuration Circuitry
• MAX II CPLD (EPM570GM100) and Flash Fast Passive Parallel (FPP)-configuration
• On-Board USB-BlasterTM II for use with the Quartus® II Programmer, Nios® II
• Software Build Tools, and System Console.
• On-Board Clocking Circuitry
• 50-MHz, 100-MHz, 125-MHz, and programmable oscillators
• SMA connector for clock input (LVPECL)
• Memory devices
• 1152-Mbyte (MB) DDR3 SDRAM with a 72-bit data bus
• 72-MB CIO RLDRAM II with a 18-bit data bus
• 4.5-MB QDRII+ SRAM with a 18-bit data bus (footprint is compatible for
• 9-Mbyte QDRII with a 18-bit data bus)
• Two 512-Mb synchronous flash with a 16-bit data bus
• Communication Ports
• PCI Express (PCIe) x8 edge connector
• Two HSMC ports
• One universal HSMC port A
• One DQS-type HSMC port B
• SMB for SDI input and output
• QSFP
• USB 2.0
• Gigabit Ethernet
• LCD header
• General User I/O
• 16 user LEDs
• Two-line character LCD display
• Six configuration status LEDs
• One transmit/receive LED (TX/RX) per HSMC interface
• Five PCI Express LEDs
• Four Ethernet LEDs
• Push Buttons and DIP Switches
• One CPU reset push button
• Three general user push buttons
• Two configuration push buttons
• Eight user DIP switches
• Four MAX V control DIP switches
• Power
• 19-V (laptop) DC input
• PCI Express edge connector power
• On-Board power measurement circuitry
• System Monitoring
• Power—voltage, current, wattage
• Temperature—FPGA die, local board
• Mechanical
• PCI Express short form factor
• PCI Express chassis or bench-top operation

More information

• Datasheet
• IC product information