Intel 5CEFA7F31I7N

Description

The Cyclone V E FPGA development board provides a hardware platform fordeveloping and prototyping low-power, high-performance, and logic-intensive designs using Altera’s Cyclone V E FPGA. The board provides a wide range of peripherals and memory interfaces to facilitate the development of Cyclone V E FPGA designs.One high-speed mezzanine card (HSMC) connector is available to add additional functionality via a variety of HSMCs available from Altera® and various partners.

Features

The development board features the following major component blocks:

• One Cyclone V E FPGA (5CEFA7F31I7N) in a 896-pin FineLine BGA (FBGA)package
• 149,500 LEs
• 56,480 adaptive logic modules (ALMs)
• 6,860 Kbit (Kb) M10K and 836 Kb MLAB memory
• Seven fractional phase locked loops (PLLs)
• 312 18x18-bit multipliers
• 480 general purpose input/output (GPIO)
• 1.1-V core voltage
• FPGA configuration circuitry
• Active Serial (AS) x1 or AS x4 configuration (EPCQ256SI16N)
• MAX® V CPLD (5M2210ZF256I5N) in a 256-pin FBGA package as the SystemController
• Flash fast passive parallel (FPP) configuration
• MAX II CPLD (EPM240M100I5N) in a 100-pin FBGA package as part of theembedded USB-BlasterTM II for use with the Quartus® II Programmer
• Clocking circuitry
• Programmable clock generator for the FPGA reference clock input
• 50-MHz single-ended oscillator for the FPGA and MAX V CPLD clock input
• 100-MHz single-ended oscillator for the MAX V CPLD configuration clockinput
• SMA input (LVDS)
• Memory
• Two 256-Mbyte (MB) DDR3 SDRAM devices with a 16-bit data bus
• One 18-Mbit (Mb) SSRAM
• One 512-Mb synchronous flash
• One 512-MB LPDDR2 SDRAM with a 32-bit data bus (only 16-bit data bus isused on this board)
• One 64-Kb I2C serial electrically erasable PROM (EEPROM)
• General user input/output
• LEDs and displays
• Four user LEDs
• One configuration load LED
• One configuration done LED
• One error LED
• Three configuration select LEDs
• Four embedded USB-Blaster II status LEDs
• Three HSMC interface LEDs
• Ten Ethernet LEDs
• Two UART data transmit and receive LEDs
• Two USB-UART interface TX / RX LEDs
• One power on LED
• One two-line character LCD display
• Push buttons
• One CPU reset push button
• One MAX V reset push button
• One program select push button
• One program configuration push button
• Four general user push buttons
• DIP switches
• Four MAX V CPLD System Controller control switches
• Two JTAG chain control DIP switches
• One fan control DIP switch
• Four general user DIP switches
• Power supply
• 14–20-V (laptop) DC input
• Mechanical
• 6.5" x 4.5" size board

More information

• Datasheet
• IC product information