Analog Devices ADIN6310 | Demoboard EVAL-ADIN6310T1LEBZ

Description

This user guide describes the ADIN6310 Field switch evaluation board with support for four 10BASE-T1L spur ports and two standard Gigabit capable Ethernet trunk ports. The hardware includes single-pair power over Ethernet (SPoE) LTC4296-1 circuit with optional serial communication classification protocol (SCCP) support. The default operation of the hardware is an unmanaged mode where the MAX32690 Arm Cortex-M4 microcontroller configures the switch into a basic switching mode and the PSE configured for Class 12 operation. Enhance the unmanaged switch operation by the DIP switch (S4), which provides ability to enable features such as time synchronization, LLDP, or IGMP snooping by default. Disable the PSE by using the DIP switch, default is enabled.

Features

• 6 port Ethernet switch ADIN6310
• 2Gb trunk ports; SGMII by SMA or ADIN1300 by RGMII
• 4 spur 10BASE-T1L ports, ADIN1100 by RGMII
• IEEE 802.3cg-compliant SPoE PSE controller, LTC4296-1
• Power Class 12
• Power classification by SCCP (not enabled)
• Arm® Cortex®-M4 microcontroller, MAX32690
• External flash and RAM
• Zephyr open source software project
• Unmanaged mode with basic switch and PSE power
• VLAN IDs 1-10 enabled on all ports
• Power coupled to 10BASE-T1L cable for all spur ports
• DIP switch options to enable other features (Time Sync, LLDP, IGMP Snooping)
• Managed mode using switch evaluation package TSN/Redundancy evaluations
• Time sensitive networking (TSN) capable
• Scheduled traffic (IEEE 802.1Qbv)
• Frame preemption (IEEE 802.1Qbu)
• Per stream filtering and policing (IEEE 802.1Qci)
• Frame replication and elimination for reliability (IEEE 802.1CB)
• IEEE 802.1AS 2020 time synchronization
• Redundancy capabilities
• High availability seamless redundancy (HSR)
• Parallel redundancy protocol (PRP)
• Media redundancy protocol (MRP)
• Host interface hardware strapping with jumpers, choice of
• Single/Dual/Quad SPI interface
• 10Mbps/100Mbps/1000Mbps Ethernet port (Port 2/Port 3)
• SGMII/100BASE-FX/1000BASE-KX
• Header for direct SPI access (Single/Dual/Quad)
• Scale port count by cascading by RJ45 or SGMII/1000BASE-KX/ 100BASE-FX
• PHY strapping by surface-mount configuration resistors
• Default state is software power down for spur Ports
• Switch firmware manages PHY operation over MDIO
• Operates from a single, external 9V to 30V supply
• LED indicators on GPIO, TIMER pins

Typical applications

• Energy automation
• Factory and process automation, Instrumentation, Building automation
• Transportation

More information

• Datasheet
• IC product information