IC-Hersteller Intel

IC-Hersteller (95)

Intel 5CGXFC5C6F27C7N

FPGA - Field Programmable Gate Array FPGA - Cyclone V GX 2908 LABs 336 IOs

Details

TopologieAufwärtswandler
Schaltfrequenz800 kHz
IC-Revision2012.12.28

Beschreibung

Altera Cyclone& 174; V 28 nm FPGAs provide the industry's lowest system cost and power, along with performance levels that make the device family ideal for differentiating your high-volume applications. You'll get up to 40 percent lower total power compared with the previous generation, efficient logic integration capabilities, integrated transceiver variants, and SoC FPGA variants with an ARM-based hard processor system (HPS). The family comes in six targeted variants: Cyclone V E FPGA with logic only Cyclone V GX FPGA with 3.125-Gbps transceivers Cyclone V GT FPGA with 5-Gbps transceivers Cyclone V SE SoC FPGA with ARM-based HPS and logic Cyclone V SX SoC FPGA with ARM-based HPS and 3.125-Gbps transceivers Cyclone V ST SoC FPGA with ARM-based HPS and 5-Gbps transceivers

Eigenschaften

  • TSMC's 28-nm low-power (28LP) process technology
  • 1.1 V core voltage
  • Wirebond low-halogen packages
  • Multiple device densities with compatible package footprints for seamless migrationbetween different device densities
  • RoHS-compliant optionsEnhanced 8-input ALM with four registers
  • M10K—10-kilobits (Kb) memory blocks with soft error correction code (ECC)
  • Memory logic array block (MLAB)—640-bit distributed LUTRAM where you canuse up to 25% of the ALMs as MLAB memory
  • Native support for up to three signal processing precision levels(three 9 x 9, two 18 x 18, or one 27 x 27 multiplier) in the samevariable-precision DSP block
  • 64-bit accumulator and cascade
  • Embedded internal coefficient memory
  • Preadder/subtractor for improved efficiencyDDR3, DDR2, and LPDDR2 with 16 and 32 bit ECC supportPCI Express® (PCIe®) Gen2 and Gen1 (x1, x2, or x4) hard IP withmultifunction support, endpoint, and root port
  • Up to 550 MHz global clock network
  • Global, quadrant, and peripheral clock networks
  • Clock networks that are not used can be powered down to reduce dynamic power
  • Precision clock synthesis, clock delay compensation, and zero delay buffering (ZDB)
  • Integer mode and fractional mode
  • 875 megabits per second (Mbps) LVDS receiver and 840 Mbps LVDS transmitter
  • 400 MHz/800 Mbps external memory interface
  • On-chip termination (OCT)
  • 3.3 V support with up to 16 mA drive strength
  • 614 Mbps to 5.0 Gbps integrated transceiver speed
  • Transmit pre-emphasis and receiver equalization
  • Dynamic partial reconfiguration of individual channels
  • Single or dual-core ARM Cortex-A9 MPCore processor-up to 800 MHz maximumfrequency with support for symmetric and asymmetric multiprocessing
  • Interface peripherals—10/100/1000 Ethernet media access control (EMAC), USB 2.0On-The-GO (OTG) controller, quad serial peripheral interface (QSPI) flash controller,NANDflash controller, Secure Digital/MultiMediaCard (SD/MMC) controller, UART,controller area network (CAN), serial peripheral interface (SPI), I2C interface, andup to 85 HPS GPIO interfaces
  • System peripherals—general-purpose timers, watchdog timers, direct memory access(DMA) controller, FPGA configuration manager, and clock and reset managers
  • On-chip RAM and boot ROM
  • HPS–FPGA bridges—include the FPGA-to-HPS, HPS-to-FPGA, and lightweightHPS-to-FPGA bridges that allow the FPGA fabric to issue transactions to slaves inthe HPS, and vice versa
  • FPGA-to-HPS SDRAM controller subsystem—provides a configurable interface tothe multiport front end (MPFE) of the HPS SDRAM controller
  • ARM CoreSight™ JTAG debug access port, trace port, and on-chip trace storage
  • Tamper protection—comprehensive design protection to protect your valuable IPinvestments
  • Enhanced advanced encryption standard (AES) design security features
  • CvP
  • Partial and dynamic reconfiguration of the FPGA
  • Active serial (AS) x1 and x4, passive serial (PS), JTAG, and fast passive parallel (FPP)x8 and x16 configuration options

Weiterführende Informationen

Artikeldaten

Artikel Nr. Daten­blatt Simu­lation Downloads ProduktserieL
(µH)
IR 1
(mA)
ISAT
(A)
RDC
(mΩ)
fres
(MHz)
H
(mm)
W
(mm)
IR
(A)
MontageartIRP,40K
(A)
ISAT1
(A)
ISAT,30%
(A)
MaterialZ @ 100 MHz
(Ω)
Zmax
(Ω)
Testbedingung ZmaxIR 2
(mA)
RDC max.
(mΩ)
Typ Muster
744311100SPEC
8 Dateien WE-HCI SMT-Hochstrominduktivität 1 4.6 85 3.8 6.9 SMT 16.8 8 19 Superflux 4.6
7440530047SPEC
8 Dateien WE-TPC SMT-Speicherdrossel 4.7 1.95 40 2.8 5.8 2.4 SMT 38
74479887310ASPEC
6 Dateien WE-PMI Power-Multilayer-Induktivität 10 600 0.125 300 20 0.8 2 SMT 850 390 High Saturation Current
742792609SPEC
8 Dateien WE-CBF SMT-Ferrit 2000 0.8 0.8 2 SMT 30 40 1000 MHz 3000 40 High Current
Artikel Nr. Daten­blatt Simu­lation
744311100SPEC
7440530047SPEC
74479887310ASPEC
742792609SPEC
Muster
Artikel Nr. Daten­blatt Simu­lation Downloads ProduktserieL
(µH)
IR 1
(mA)
ISAT
(A)
RDC
(mΩ)
fres
(MHz)
H
(mm)
W
(mm)
IR
(A)
MontageartIRP,40K
(A)
ISAT1
(A)
ISAT,30%
(A)
MaterialZ @ 100 MHz
(Ω)
Zmax
(Ω)
Testbedingung ZmaxIR 2
(mA)
RDC max.
(mΩ)
Typ Muster