Texas Instruments TPS259261DRCR | Demoboard TIDA-010128

Description

This reference design describes a 20.8 GSPS sampling system using RF sampling analog-to-digital converters (ADCs) in time interleaved configuration. Time interleaving method is a proven and traditional way of increasing sample rate, however, matching individual ADCs offset, gain and sampling time mismatch is critical to achieve performance. The complexity of interleaving increases with higher sampling clock. The phase matching between the ADCs is one of the critical specifications to achieve better SFDR and ENOB. This reference design uses the noiseless aperture delay adjustment feature on ADC12DJ5200RF with a 19 fs precise phase control steps that eases 20.8 GSPS interleaving implementation. The reference design uses on-board low noise JESD204B clock generator based on LMK04828 and LMX2594 that meets 12 bit system performance requirement.

Features

• 20.8 GSPS Time interleaved 12-bit RF-sampling ADCs
• 6 GHz Analog front end
• Fine sample clock phase adjustment (19 fs resolution)
• Phase synchronization of multiple ADCs
• Companion power reference design with a >85% efficiency at 12-V input
• JESD204B supporting 8, 16, or 32 JESD lanes, data rates up to 12.8 Gbps per lane

Typical applications

• Notebooks, Desktops, and Servers / Copiers and Printers
• Telecom and Datacom / Base Stations
• Memory Termination Regulator for DDR, DDR2, DDR3, DDR3L, Low-Power DDR3 and DDR4

More information

• Datasheet
• IC product information