Texas Instruments TLV70233DBVT | Demoboard TIDA-01028

Description

This reference design provides a practical example of interleaved RF-sampling analog-to-digital converters (ADCs) to achieve a 12.8-GSPS sampling rate. This is achieved by time-terleaving two RF-sampling ADCs. Interleaving requires a phase shift between the ADCs, which this reference design achieves using the Noiseless Aperture Delay Adjustment (tAD Adjust) feature of the ADC12DJ3200. This feature is also used to minimize mismatches typical of interleaved ADCs: maximizing SNR, ENOB, and SFDR performance. A low phase noise clocking tree with JESD204B support is also featured on this reference design, and it is implemented using the LMX2594 wideband PLL and the LMK04828 synthesizer and jitter cleaner.

Features

• Very Low Dropout:– 37 mV at IOUT = 50 mA, VOUT = 2.8 V– 75 mV at IOUT = 100 mA, VOUT = 2.8 V– 220mV at IOUT = 300 mA, VOUT = 2.8 V
• 2% Accuracy
• Low IQ: 35 μA
• Fixed-Output Voltage Combinations Possible from 1.2 V to 4.8 V
• High PSRR: 68 dB at 1 kHz
• Stable With Effective Capacitance of 0.1 μF(1)
• Thermal Shutdown and Overcurrent Protection
• Packages: 5-Pin SOT-23 and 1.5-mm × 1.5-mm, 6-Pin WSON

Typical applications

• ZigBee® Networks
• Wireless Handsets / Smart Phones / Bluetooth® Devices / Li-Ion Battery-Operated Handheld Products
• WLAN and Other PC Add-on Cards

More information

• Datasheet
• IC product information