| Topology | Other Topology |
| IC revision | E4 |
This verified reference design provides an overview on how to implement a three-level three-phase SiC based DC:AC grid-tie inverter stage.Higher switching frequency of 50KHz reduces the size of magnetics for the filter design and enables higher power density. The use of SiC MOSFETs with switching loss ensures higher DC bus voltages of up to 1000V and lower switching losses with a peak efficiency of 99 percent. This design is configurable to work as a two-level or three-level inverter.The system is controlled by a single C2000 microcontroller (MCU), TMS320F28379D, which generates PWM waveforms for all power electronic switching devices under all operating modes.
Order Code | Datasheet | Simulation | Downloads | Status | Product series | C | Tol. C | VR(V (DC)) | Size | Operating Temperature | DF(%) | RISO | Ceramic Type | L(mm) | W(mm) | H(mm) | Fl(mm) | Packaging | Pins | Type | Mount | IR(A) | Working Voltage(V (AC)) | Samples | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| WCAP-CSGP MLCCs 50 V(DC), 100 nF, ±10% | Status Activei| Production is active. Expected lifetime: >10 years. | Product seriesWCAP-CSGP MLCCs 50 V(DC) | Capacitance100 nF | Capacitance±10% | Rated Voltage50 V (DC) | Size0603 | Operating Temperature -55 °C up to +125 °C | Dissipation Factor3 % | Insulation Resistance5 GΩ | Ceramic TypeX7R Class II | Length1.6 mm | Width0.8 mm | Height0.8 mm | Pad Dimension0.4 mm | Packaging7" Tape & Reel | – | – | – | – | – | |||||
![]() | WR-PHD Pin Header - Single, –, – | Simulation– | Downloads7 files | Status Activei| Production is active. Expected lifetime: >10 years. | Product seriesWR-PHD Pin Header - Single | – | – | – | – | Operating Temperature -40 °C up to +105 °C | – | Insulation Resistance1000 MΩ | – | Length10.16 mm | – | – | – | PackagingBag | Pins4 | TypeAngled | MountTHT | Rated Current3 A | Working Voltage250 V (AC) |