Texas Instruments SN74AVC4T774PWR | Demoboard TIDA-01028

Description

This reference design provides a practical example of interleaved RF-sampling analog-to-digital converters (ADCs) to achieve a 12.8-GSPS sampling rate. This is achieved by time-terleaving two RF-sampling ADCs. Interleaving requires a phase shift between the ADCs, which this reference design achieves using the Noiseless Aperture Delay Adjustment (tAD Adjust) feature of the ADC12DJ3200. This feature is also used to minimize mismatches typical of interleaved ADCs: maximizing SNR, ENOB, and SFDR performance. A low phase noise clocking tree with JESD204B support is also featured on this reference design, and it is implemented using the LMX2594 wideband PLL and the LMK04828 synthesizer and jitter cleaner.

Features

• Each Channel Has an Independent DIR Control Input
• Control Inputs VIH/VIL Levels are Referenced toVCCA Voltage
• Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.2-V to 3.6-VPower-Supply Range
• I/Os are 4.6-V Tolerant
• Ioff Supports Partial Power-Down-Mode Operation
• Typical Data Rates– 380 Mbps (1.8-V to 3.3-V Translation)– 200 Mbps (<1.8-V to 3.3-V Translation)– 200 Mbps (Translate to 2.5 V or 1.8 V)– 150 Mbps (Translate to 1.5 V)– 100 Mbps (Translate to 1.2 V)
• Latch-Up Performance Exceeds 100 mA PerJESD 78, Class II
• ESD Protection Exceeds the Following Levels(Tested Per JESD 22)– ±8000-V Human-Body Model (A114-A)– 250-V Machine Model (A115-A)– ±1500-V Charged-Device Model (C101)

Typical applications

• Telecom
• Personal Electronic
• Industrial / Enterprise

More information

• Datasheet
• IC product information