Texas Instruments LMH6401IRMZR | Demoboard TIDA-01028

Description

This reference design provides a practical example of interleaved RF-sampling analog-to-digital converters (ADCs) to achieve a 12.8-GSPS sampling rate. This is achieved by time-terleaving two RF-sampling ADCs. Interleaving requires a phase shift between the ADCs, which this reference design achieves using the Noiseless Aperture Delay Adjustment (tAD Adjust) feature of the ADC12DJ3200. This feature is also used to minimize mismatches typical of interleaved ADCs: maximizing SNR, ENOB, and SFDR performance. A low phase noise clocking tree with JESD204B support is also featured on this reference design, and it is implemented using the LMX2594 wideband PLL and the LMK04828 synthesizer and jitter cleaner.

Features

• Sampling rate up to 12.8GSPS, using timeinterleaved 12-bit RF-sampling ADCs
• Analog front end support up to 6-GHz bandwidth
• Fine sample clock phase adjustment (19 fs resolution)
• Phase synchronization of multiple ADCs
• Companion power reference design with a >85% efficiency at 12-V input
• JESD204B supporting 8, 16, or 32 JESD lanes, data rates up to 12.8 Gbps per lane

Typical applications

• Ultra-Wideband ADC Drivers / Communications Receivers / RF Sampling Subsystems / SAW Filter Buffers and Drivers
• Defense and Radar
• Test and Measurement

More information

• Datasheet
• IC product information