Texas Instruments TPS7A8400RGRR | Demoboard TIDA-01028

Description

This reference design provides a practical example of interleaved RF-sampling analog-to-digital converters (ADCs) to achieve a 12.8-GSPS sampling rate. This is achieved by time-terleaving two RF-sampling ADCs. Interleaving requires a phase shift between the ADCs, which this reference design achieves using the Noiseless Aperture Delay Adjustment (tAD Adjust) feature of the ADC12DJ3200. This feature is also used to minimize mismatches typical of interleaved ADCs: maximizing SNR, ENOB, and SFDR performance. A low phase noise clocking tree with JESD204B support is also featured on this reference design, and it is implemented using the LMX2594 wideband PLL and the LMK04828 synthesizer and jitter cleaner.

Features

• Low Dropout: 180 mV (max) at 3 A
• 1% (max) Accuracy Over Line, Load, and Temperature
• Excellent Load Transient Response
• Adjustable Soft-Start In-Rush Control

Typical applications

• Instrumentation, Medical, and Audio / Test and Measurement
• Digital Loads: SerDes, FPGAs, and DSPs / High-Speed Analog Circuits / Imaging: CMOS Sensors and Video ASICs

More information

• Datasheet
• IC product information