Texas Instruments TPS7A3301RGWT | Demoboard TIDA-01028

Description

This reference design provides a practical example of interleaved RF-sampling analog-to-digital converters (ADCs) to achieve a 12.8-GSPS sampling rate. This is achieved by time-terleaving two RF-sampling ADCs. Interleaving requires a phase shift between the ADCs, which this reference design achieves using the Noiseless Aperture Delay Adjustment (tAD Adjust) feature of the ADC12DJ3200. This feature is also used to minimize mismatches typical of interleaved ADCs: maximizing SNR, ENOB, and SFDR performance. A low phase noise clocking tree with JESD204B support is also featured on this reference design, and it is implemented using the LMX2594 wideband PLL and the LMK04828 synthesizer and jitter cleaner.

Features

• Input Voltage Range: –3 V to –36 V
• Adjustable Output: –1.18 V to –33 V
• Stable With Ceramic Capacitors ≥ 10 μF
• Built-In Current-Limit and Thermal Shutdown Protection
• Available in an External Heatsink-Capable, HighThermal Performance TO-220 Package

Typical applications

• Test and Measurement
• Post DC-DC Converter Regulation and Ripple Filtering
• Audio
• Supply Rails for Operational Amplifiers, DACs, ADCs, and Other High-Precision Analog Circuitry
• Medical

More information

• Datasheet
• IC product information