Texas Instruments LMX2594RHAR | Demoboard TIDA-01028

Description

This reference design provides a practical example of interleaved RF-sampling analog-to-digital converters (ADCs) to achieve a 12.8-GSPS sampling rate. This is achieved by time-terleaving two RF-sampling ADCs. Interleaving requires a phase shift between the ADCs, which this reference design achieves using the Noiseless Aperture Delay Adjustment (tAD Adjust) feature of the ADC12DJ3200. This feature is also used to minimize mismatches typical of interleaved ADCs: maximizing SNR, ENOB, and SFDR performance. A low phase noise clocking tree with JESD204B support is also featured on this reference design, and it is implemented using the LMX2594 wideband PLL and the LMK04828 synthesizer and jitter cleaner.

Features

• 10-MHz to 15-GHz output frequency
• –110 dBc/Hz phase noise at 100-kHz offset with 15-GHz carrier
• 45-fs rms jitter at 7.5 GHz (100 Hz to 100 MHz)
• Programmable output power
• PLL key specifications– Figure of merit: –236 dBc/Hz– Normalized 1/f noise: –129 dBc/Hz– High phase detector frequency– 400-MHz integer mode– 300-MHz fractional mode– 32-bit fractional-N divider
• Remove integer boundary spurs withprogrammable input multiplier
• Synchronization of output phase across multipledevices
• Support for SYSREF with 9-ps resolutionprogrammable delay
• Frequency ramp and chirp generation ability forFMCW applications
• < 20-μs VCO calibration speed
• 3.3-V single power supply operation

Typical applications

• 5G and mm-Wave wireless infrastructure / Radar / MIMO / Phased array antennas and beam forming
• High-speed data converter clocking (supports JESD204B)
• Test and measurement equipment

More information

• Datasheet
• IC product information