Texas Instruments LMX2594RHAR | Demoboard TIDA-010122

Description

This reference design provides the solution for synchronization design challenges associated with emerging 5G adapted applications like massive multiple input multiple output (mMIMO), phase array RADAR and communication payload. The typical RF front end contains antenna, low noise amplifier (LNA), mixer , local oscillator (LO) in analog domain and analog to digital converter, numerical controlled oscillator (NCO) and digital down converter (DDC) in digital domain. To achieve overall system synchronization these digital blocks need to be synchronize with system clock. This reference design uses ADC12DJ3200 data converter, achieve less than 5-ps channel-to-channel skew across multiple receiver with deterministic latency by synchronizing on chip NCO with SYNC~ and uses noiseless aperture delay adjustment (tAD Adjust) feature to further reduce skew. This design also provides a very low phase noise clocking solution based the LMX2594 wide band PLL and the LMK04828 synthesizer and jitter cleaner.

Features

• 10-MHz to 15-GHz output frequency
• –110 dBc/Hz phase noise at 100-kHz offset with15-GHz carrier
• 45-fs rms jitter at 7.5 GHz (100 Hz to 100 MHz)
• Programmable output power
• PLL key specifications– Figure of merit: –236 dBc/Hz– Normalized 1/f noise: –129 dBc/Hz– High phase detector frequency– 400-MHz integer mode– 300-MHz fractional mode– 32-bit fractional-N divider
• Remove integer boundary spurs withprogrammable input multiplier
• Synchronization of output phase across multipledevices
• Support for SYSREF with 9-ps resolutionprogrammable delay
• Frequency ramp and chirp generation ability forFMCW applications
• < 20-μs VCO calibration speed
• 3.3-V single power supply operation

Typical applications

• 5G and mm-Wave wireless infrastructure / Radar / MIMO / Phased array antennas and beam forming
• High-speed data converter clocking (supports JESD204B)
• Test and measurement equipment

More information

• Datasheet
• IC product information