AnDAPT Inc AmP8DB6QF65 | Demoboard ARD_X_AUP_A1

Description

The ARD_X_AUP_A1 is a scalable power supply designed to provide power to Xilinx Artix UltraScale+ Cost-optimized FPGA devices using minimum number of power rails. The designs are scalable to support the cost- and power-optimized FPGA devices including AU10P, AU15P, AU20P, and AU25P.

Features

• Design supplies all 10 voltage rails (Figure 1) to Xilinx Artix UltraScale+ FPGA using one AnDAPT PMIC (Table 1) containing-
• Four async buck switchers (C150) of 6 A capacity each
• Two LDOs (C710) of 2 A capacity each
• Two load switches (C750) of 6 A capacity each
• Inbuilt sequencer (C420) meeting Xilinx turn-on and turnoff timing requirements
• Soft start/shut-down
• Only one input of 12 V (±10%) required
• Adjustable output voltage with down to 2.4 mV resolution
• 1% voltage accuracy
• Efficiency up to 90%
• QFN 5x5 sq. mm package
• Protections:Input Undervoltage Lockout (ViUVLO), Output Under voltage Lockout (VoUVLO), Overcurrent Protection (OCP), Output Overvoltage Protection (OVP), Overtemperature Protection (OTP), Short-circuit Protection (SCP)
• Easy to change any voltage, currents or sequencing (if required) including enable/disable rails using web-basedWebAmp R.D software

Typical applications

• Industrial IoT/Factory automation
• Secure networking
• Machine vision/Image processing, 4k broadcast/Video processing

More information

• IC product information