Dominic Büchone of our experts regarding the topic Basic Design Guide, answers your technical questions from the webinar "Basic Design Guide".

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Conductor width and conductor spacing on outer layers: What is the minimum track and gap that may be used, relative to the chosen final copper thickness?

The minimum manufacturable track and gap depends mainly on the copper thickness. On the outer layers, the final copper layer thickness is composed of base copper (usually a copper foil) and galvanised copper. For thick layers of copper, the required gap width is larger than the required track width.

This is necessary to allow for sufficient etch compensation, i.e. the printed circuit board manufacturer widens the tracks so that after the etching process, the nominal dimension of the design data will be achieved.

The respective standard values are listed in a table in the Basic Design Guide.

Conductor width and conductor spacing on outer layers: What is the maximum final copper thickness when using 75µm track widths and / or 75µm gaps?

A reliable etching process for 75µm structures is only possible with thin copper thicknesses (maximum 25 - 30µm).

Printed circuit boards with plated-through holes always require additional processes in order to deposit enough copper in the holes and also to reduce the copper build-up on the surface compared with the standard. Due to cost implications, fine conductive patterns significantly smaller than 100µm should only be used when absolutely necessary.

Conductor width and conductor spacing on inner layers: What is the minimum track and gap that should be adhered to relative to the chosen final copper thickness?

The minimum manufacturable track and gap width depends mainly on the copper thickness.

The inner layers usually consist solely of the copper coating of the cores (base copper). Only when using buried vias does the final copper thickness include base copper and galvanised copper.

For thick layers of copper, the required gap width is larger than the required track width. This is necessary to allow for sufficient etch compensation, i.e. the printed circuit board manufacturer widens the tracks so that after the etching process, the nominal dimension of the design data will be achieved.

The respective standard values are listed in a table in the Basic Design Guide.

Conductor width and conductor spacing on inner layers: What is the maximum final copper thickness when using 75µm track widths and / or 75µm gaps?

A reliable etching process for 75µm structures is only possible with thin copper thicknesses (maximum 25 - 30µm). For the inner layers, this usually means 17.5µm (1/2 oz.) base copper is used.

Final copper thickness on outer layers: What standard final copper thicknesses can be used?

On the outer layers, the final copper layer thickness is composed of base copper (usually a copper foil) and galvanised copper. If there are no special requirements, a 17.5 micron copper foil will be used and the resulting final copper thickness is approx. 50µm including the galvanised copper.

With 35µm and 70µm base copper, respective final copper thicknesses of 70µm and 105µm are produced, however modified conductive pattern parameters must be taken into account. These can be found in the Basic Design Guide.

For fine conductive patterns significantly smaller than 100µm, the final copper thickness must be limited to a maximum of 25 - 30µm. The fine conductive patterns are achieved by thinner copper foils and special processes.

Final copper thickness on inner layers: What standard final copper thicknesses can be used?

On the inner layers, the final copper thickness is equal to the copper coating of the cores (base copper). Only when using buried vias does the final copper thickness consist of base copper and the galvanised copper.

The copper claddings commonly used are 17.5µm and 35µm.

For special requirements, 70µm or 105µm are also possible, but modified conductive pattern parameters are required. These can be found in the Basic Design Guide.

Through hole vias: What is the minimum pad size that can be used for through hole vias?

For standard PCB thickness up to 2 mm, the standard via pad size is 0.55 / 0.60 mm.

For cost and reliability reasons, our recommendation is the bigger, the better. At higher packing density, it is often required to reduce the pad sizes, and thus reduce the bore diameter.

However drill diameters that are too small can result in reliability issues. Therefore, it is not possible to reduce the Viapads arbitrarily. 0.50mm pad sizes are still acceptable for most applications. Smaller pad sizes are only possible with layer structures with low complexity, ie relatively few layers, board thickness max. 1.60 mm, and ideally not using very thin cores.

The respective standard values are listed in the Basic Design Guide.

Plated through hole vias: What final drill diameter is acceptable when using a specified pad size?

Usually the final drill diameter is specified to be 0.35mm smaller than the pad size.

The PCB manufacturer usually drills 0.10mm greater than the specified final diameter and uses a theoretical residual ring of min. 125µm, based on the tool diameter. Thus, a drill diameter of 0.15 mm is appropriate for a 0.55mm via pad.

The respective standard values are listed in the Basic Design Guide.

Plated through hole vias: What are the copper clearances that should be adhered to on inner ground layers, depending on the selected pad sizes?

Due to manufacturing tolerances, in particular the dimensional variations of thinner cores, an adequate isolation distance of 225µm around the via drilling in design is recommended.

This ensures that the final product does not have isolation distances that are too small. Approximately, the same size is recommended if the pads on the signal inner layers, which are not connected, are removed.

The respective standard values are listed in the Basic Design Guide.

Plated through hole vias: What soldermask clearances are recommended for the vias depending on the chosen pad size?

For quality and reliability reasons, it is recommended that the vias in the solder mask have larger clearances than the hole diameter, especially the small vias. This is largely avoided as in some cases the vias remain sealed with mask and the chemical residues can rise onto the solder surface and result in poor solderability.

For the recommended sizes, please refer to the table in the Basic Design Guide.

Solder mask: What soldermask clearances should be used for solder pads?

As for the soldermask process, fitting tolerances must be considered, so that the soldermask clearance should always be larger than the solder pads. This is the only way to ensure that the entire pad remains free of solder resist and optimum soldering results can be achieved.

Another important function of the solder mask is to cover all traces, i.e. to isolate. Therefore, the clearances in densely packaged designs cannot be increased arbitrarily. The surrounding clearance should usually be half the conductor spacing width . Only when using fine conductive patterns under 100µm can the soldermask clearance be reduced to below 50µm.

This process considerably increases the production cost. The smallest possible clearance is 35µm and through this 75µm conductor spacings can then be achieved. The respective values are listed in the Basic Design Guide.

Adaptation of soldermask clearances can be performed on request by the board manufacturer.

Solder mask: What is the minimum soldermask web width allowed?

Depending on the process and materials, a minimum soldermask web width of 70µm can be reliably produced. Due to this, it is also possible to produce 0.40mm pitch QFP components with a soldermask web between all pads.

Other design parameters – conductive pattern: What distance should the outer contour of the board be from the conductive pattern/copper in the design?

The minimum distance between the conductive pattern/copper and outer PCB edge depends on the contour machining technology used. Generally, a sufficient distance, taking into account all the tolerances, is required to avoid milling off copper. This would creates burrs and result in the PCB surfaces being scratched in all subsequent processes when the circuit boards are laid on top of one another.

If the printed circuit boards are milled, burring can be avoided by designing a conductive pattern with at least 0.23 mm distance to the contour.

For V Scoring the required value depends on the PCB thickness. The thicker the PCB, the deeper the 30° scoring tool must cut and more material at the surface in the x and y dimension will be cut away. As a guideline, for 1.60 mm standard PCB thickness, a distance of at least 0.45mm between the copper and the board edge, will avoid the risk of a ridge forming in the conductive pattern.

Please note that due to the tolerance for the PCB edge, the edge achieved may be smaller than the nominal size.

Other design parameters – conductive pattern: What distance between the conductor pattern and the NPTH holes should be adhered to in the design?

To avoid drilling the conductor pattern, resulting in burrs and exposed copper, a minimum distance of 0.25mm from the conductor pattern to the bore wall of NPTH holes should be respected.

Please note that depending on the tolerance field for the hole diameter of the drill holes may also be larger than the nominal size drilled.

Other design parameters - legend print: What is the minimum line width and text height that should be used in the design?

To ensure that the legend print is legible, a minimum line width of 100µm and a minimum text height of 1.50mm should be respected. Depending on the font, thick lines can lead to poorer legibility.

Very thick layers of copper on the PCB surface create large "bumps", therefore, broader text should be used.

Other design parameters - legend print: What distance between legend print and soldermask openings should be adhered to in the design?

In order to avoid that pads are partially overprinted, considering all other tolerances, a distance of at least 100µm between the legend print and the soldermask openings should be used.

The reasoning behind this is that the solder mask openings are at least 50µm larger than the solder pads. Printing on to the pads could have a negative impact on the soldering quality.